dc.contributor.author | Wolfmann, Aaron Gustavo | |
dc.contributor.author | De Giusti, Armando | |
dc.date.accessioned | 2022-07-29T15:27:38Z | |
dc.date.available | 2022-07-29T15:27:38Z | |
dc.date.issued | 2014 | |
dc.identifier.issn | 1-60132-282-8 | |
dc.identifier.uri | http://hdl.handle.net/11086/27712 | |
dc.description.abstract | The Symmetric Multiprocessors architecture is composed by a complex set of cores, chips and memory channels that make it difficult to implement a parallel program that efficiently uses all resources. Another obstacle for
achieving a performance according the resources is added by algorithms with hard data dependency. Asynchronicity is a key
to get all processors running. Petri Nets have been used for a long time to model algorithms, but not as a tool to parallel execution. In this paper we introduce an asynchronous Parallel Execution
Model based on Petri Nets and the process to go from a high level model to an executable parallel program. The Cholesky
Factorization algorithm is used as a testbed. Tests results yield values that are near the theoretical peak and open good prospects
to expand the model to other environments and algorithms. | es |
dc.format.medium | Impreso | |
dc.language.iso | eng | es |
dc.rights | Attribution-NonCommercial-ShareAlike 4.0 International | * |
dc.rights.uri | https://creativecommons.org/licenses/by-nc-sa/4.0/ | * |
dc.subject | Cholesky Factorization Algorithm | es |
dc.subject | Cores | es |
dc.subject | Chips | es |
dc.subject | Memory channels | es |
dc.title | Petri net based algorithm modelization and parallel execution on symmetric multiprocessors | es |
dc.type | conferenceObject | es |
dc.description.fil | Fil: Wolfmann, Aaron Gustavo. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales. Laboratorio de Computación; Argentina. | es |
dc.description.fil | Fil: De Giusti, Armando. Universidad Nacional de La Plata. Facultad de Informática; Argentina. | es |
dc.description.field | Otras Ingeniería Eléctrica, Ingeniería Electrónica e Ingeniería de la Información | |
dc.conference.city | Las Vegas - USA | |
dc.conference.country | Estados Unidos | |
dc.conference.editorial | CSREA Press | |
dc.conference.event | The 2014 Conf. on Parallel and Distributed Processing - PDPTA 2014 | |
dc.conference.eventcity | Las Vegas | |
dc.conference.eventcountry | Estados Unidos | |
dc.conference.eventdate | 2014-7 | |
dc.conference.institution | World Academy of Science | |
dc.conference.journal | Proceedings of The 2014 Conf. on Parallel and Distrib. Processing - PDPTA 2014 | |
dc.conference.publication | Libro | |
dc.conference.work | Artículo Completo | |
dc.conference.type | Congreso | |